Download or Read online Verification Techniques for System Level Design full in PDF, ePub and kindle. this book written by Masahiro Fujita and published by Morgan Kaufmann which was released on 27 July 2010 with total page 256 pages. We cannot guarantee that Verification Techniques for System Level Design book is available in the library, click Get Book button and read full online book in your kindle, tablet, IPAD, PC or mobile whenever and wherever You Like. This book will explain how to verify SoC (Systems on Chip) logic designs using “formal and “semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. • First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs. • Formal verification of high-level designs (RTL or higher). • Verification techniques are discussed with associated system-level design methodology.
Verification Techniques for System Level Design
- Author : Masahiro Fujita
- Publisher : Morgan Kaufmann
- Pages : 256 pages
- ISBN : 9780080553139
- Release : 27 July 2010
- Rating : 3/5 from 2 reviews